`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   00:34:31 06/22/2015
// Design Name:   MainControl
// Module Name:   D:/Libraries/Documents/Ingenieria en Comp/MIPS/trunk/Final-Mips/MainCUTest.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: MainControl
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module MainCUTest;

	// Inputs
	reg [5:0] op;

	// Outputs
	wire RegDst;
	wire RegWrite;
	wire ALUSrc;
	wire PCSrc;
	wire MemRead;
	wire [3:0] MemWrite;
	wire MemToReg;
	wire [1:0] ALUOp;
	wire jmp;
	wire [2:0] LoadOp;
	wire [1:0] StoreOp;
	wire [2:0] InmCtrl;

	// Instantiate the Unit Under Test (UUT)
	MainControl uut (
		.op(op), 
		.RegDst(RegDst), 
		.RegWrite(RegWrite), 
		.ALUSrc(ALUSrc), 
		.PCSrc(PCSrc), 
		.MemRead(MemRead), 
		.MemWrite(MemWrite), 
		.MemToReg(MemToReg), 
		.ALUOp(ALUOp), 
		.jmp(jmp), 
		.LoadOp(LoadOp), 
		.StoreOp(StoreOp),
		.InmCtrl(InmCtrl)
	);

	initial begin
		// Initialize Inputs
		op = 0;

		// Wait 100 ns for global reset to finish
		#100;
      //Cambiamos a un LOAD WORD
		op = 6'b 100011;
		#100;
		//STORE
		op = 6'b 101011;
		#100;
		//LOAD UHW
		op = 6'b 100101;
		#100;
		//STORE BYTE
		op = 6'b 101000;
		#100;
		//OP con Inm
		op = 6'b 001100; //And
		#100;
		//OP con Inm
		op = 6'b 001111; //LUI
		#100;
		//Branch E
		op = 6'b 000100;
		#100;
		//Branch NE
		op = 6'b 000101;
		

	end
      
endmodule

